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feat(h4mp): update breaking soc headers(part2)

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This commit is contained in:
Chen Jichang
2025-08-14 14:16:06 +08:00
parent 70fb18be3e
commit f8480a115a
21 changed files with 14207 additions and 76 deletions
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1
Kconfig
View File

@@ -151,6 +151,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
default "y" if IDF_TARGET="esp32h4"
select IDF_TARGET_ARCH_RISCV
select IDF_ENV_BRINGUP
select IDF_ENV_FPGA if ESP32H4_SELECTS_REV_MP
config IDF_TARGET_LINUX
bool

11
components/esp_hw_support/port/esp32h4/Kconfig.hw_support
View File

@@ -1,3 +1,14 @@
comment "NOTE! Support of ESP32-H4 MP is mutually exclusive"
comment "Read the help text of the option below for explanation"
config ESP32H4_SELECTS_REV_MP
bool "Select ESP32-H4 MP version"
default n
help
Enable this option to select ESP32-H4 MP revision.
MP revisions have some hardware differences with Beta revision.
MP revisions is not compatible with Beta revision.
choice ESP32H4_REV_MIN
prompt "Minimum Supported ESP32-H4 Revision"
default ESP32H4_REV_MIN_0

40
components/soc/CMakeLists.txt
View File

@@ -4,11 +4,19 @@ set(target_folder "${target}")
# On Linux the soc component is a simple wrapper, without much functionality
if(NOT ${target} STREQUAL "linux")
set(srcs "lldesc.c"
"dport_access_common.c"
"${target_folder}/interrupts.c"
"${target_folder}/gpio_periph.c"
"${target_folder}/uart_periph.c")
if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
set(srcs "lldesc.c"
"dport_access_common.c"
"${target_folder}/interrupts_beta5.c"
"${target_folder}/gpio_periph.c"
"${target_folder}/uart_periph.c")
else()
set(srcs "lldesc.c"
"dport_access_common.c"
"${target_folder}/interrupts.c"
"${target_folder}/gpio_periph.c"
"${target_folder}/uart_periph.c")
endif()
endif()
set(includes "include" "${target_folder}")
@@ -16,6 +24,13 @@ set(includes "include" "${target_folder}")
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
# miscellaneous headers, like definitions, man-made register headers, wrappers, etc.
list(APPEND includes "${target_folder}/include")
if(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
if(CONFIG_ESP32H4_SELECTS_REV_MP)
list(APPEND includes "${target_folder}/include/hw_ver_mp")
else()
list(APPEND includes "${target_folder}/include/hw_ver_beta5")
endif()
endif()
endif()
# register headers that generated by script from CSV
@@ -25,13 +40,20 @@ if(CONFIG_IDF_TARGET_ESP32P4)
else()
list(APPEND includes "${target_folder}/register/hw_ver2")
endif()
elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H4 IDF-13835
elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H21 IDF-13923
list(APPEND includes "${target_folder}/register")
if(CONFIG_ESP32H21_SELECTS_REV_MP)
list(APPEND includes "${target_folder}/register/hw_ver_mp")
else()
list(APPEND includes "${target_folder}/register/hw_ver_beta1")
endif()
elseif(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
list(APPEND includes "${target_folder}/register")
if(CONFIG_ESP32H4_SELECTS_REV_MP)
list(APPEND includes "${target_folder}/register/hw_ver_mp")
else()
list(APPEND includes "${target_folder}/register/hw_ver_beta5")
endif()
else()
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
list(APPEND includes "${target_folder}/register")
@@ -210,5 +232,9 @@ if(target STREQUAL "esp32")
endif()
if(NOT CONFIG_IDF_TARGET_LINUX)
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.beta5.ld")
else()
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
endif()
endif()

0
components/soc/esp32h4/include/soc/interrupts.h → components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h
View File

124
components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h Normal file
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@@ -0,0 +1,124 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURCE,
ETS_BT_BB_INTR_SOURCE,
ETS_BT_BB_NMI_SOURCE,
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MST_INTR_SOURCE,
ETS_ZB_MAC_INTR_SOURCE,
ETS_MODEM_APB_TIMEOUT_INTR_SOURCE,
ETS_BT_MAC_INT1_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE,
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_RTC_BLE_TIMER_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_TOUCH_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_LP_PERI_PMS_INTR_SOURCE,
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
ETS_BUS_MONITOR_INTR_SOURCE,
ETS_CORE0_TRACE_INTR_SOURCE,
ETS_CORE1_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTERRUPT_PRO_SOURCE,
ETS_GPIO_INTERRUPT_2_SOURCE,
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_HP_MEM_APM_M0_INTR_SOURCE,
ETS_HP_MEM_APM_M1_INTR_SOURCE,
ETS_HP_MEM_APM_M2_INTR_SOURCE,
ETS_HP_MEM_APM_M3_INTR_SOURCE,
ETS_CPU_APM_M0_INTR_SOURCE,
ETS_CPU_APM_M1_INTR_SOURCE,
ETS_CPU_APM_M2_INTR_SOURCE,
ETS_CPU_APM_M3_INTR_SOURCE,
ETS_HP_PERI_PMS_INTR_SOURCE,
ETS_MODEM_PERI_PMS_INTR_SOURCE,
ETS_CPU_PERI_PMS_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE,
ETS_TWAI0_INTR_SOURCE,
ETS_TWAI0_TIMER_INTR_SOURCE,
ETS_USB_SERIAL_JTAG_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_I2C_EXT0_INTR_SOURCE,
ETS_I2C_EXT1_INTR_SOURCE,
ETS_TG0_T0_INTR_SOURCE,
ETS_TG0_WDT_INTR_SOURCE,
ETS_TG1_T0_INTR_SOURCE,
ETS_TG1_WDT_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_APB_ADC_INTR_SOURCE,
ETS_PWM0_INTR_SOURCE,
ETS_PWM1_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_USB_OTG11_INTR_SOURCE,
ETS_ASRC_CHNL0_INTR_SOURCE,
ETS_ASRC_CHNL1_INTR_SOURCE,
ETS_ZERO_DET_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE,
ETS_DMA_IN_CH1_INTR_SOURCE,
ETS_DMA_IN_CH2_INTR_SOURCE,
ETS_DMA_IN_CH3_INTR_SOURCE,
ETS_DMA_IN_CH4_INTR_SOURCE,
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH3_INTR_SOURCE,
ETS_DMA_OUT_CH4_INTR_SOURCE,
ETS_GPSPI2_INTR_SOURCE,
ETS_GPSPI3_INTR_SOURCE,
ETS_AES_INTR_SOURCE,
ETS_SHA_INTR_SOURCE,
ETS_ECC_INTR_SOURCE,
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif

144
components/soc/esp32h4/interrupts.c
View File

@@ -29,72 +29,80 @@ const char *const esp_isr_names[] = {
[19] = "LP_WDT",
[20] = "TOUCH",
[21] = "HUK",
[22] = "CPU_FROM_CPU_0",
[23] = "CPU_FROM_CPU_1",
[24] = "CPU_FROM_CPU_2",
[25] = "CPU_FROM_CPU_3",
[26] = "BUS_MONITOR",
[27] = "CORE0_TRACE",
[28] = "CORE1_TRACE",
[29] = "CACHE",
[30] = "CPU_PERI_TIMEOUT",
[31] = "GPIO_INTERRUPT_PRO",
[32] = "GPIO_INTERRUPT_2",
[33] = "PAU",
[34] = "HP_PERI_TIMEOUT",
[35] = "HP_APM_M0",
[36] = "HP_APM_M1",
[37] = "HP_APM_M2",
[38] = "HP_APM_M3",
[39] = "HP_APM_M4",
[40] = "CPU_APM_M0",
[41] = "CPU_APM_M1",
[42] = "CPU_APM_M2",
[43] = "CPU_APM_M3",
[44] = "MSPI",
[45] = "I2S",
[46] = "UHCI0",
[47] = "UART0",
[48] = "UART1",
[49] = "LEDC",
[50] = "TWAI0",
[51] = "TWAI0_TIMER",
[52] = "USB_SERIAL_JTAG",
[53] = "RMT",
[54] = "I2C_EXT0",
[55] = "I2C_EXT1",
[56] = "TG0_T0",
[57] = "TG0_WDT",
[58] = "TG1_T0",
[59] = "TG1_WDT",
[60] = "SYSTIMER_TARGET0",
[61] = "SYSTIMER_TARGET1",
[62] = "SYSTIMER_TARGET2",
[63] = "APB_ADC",
[64] = "PWM0",
[65] = "PWM1",
[66] = "PCNT",
[67] = "PARL_IO_TX",
[68] = "PARL_IO_RX",
[69] = "USB_OTG11",
[70] = "ASRC_CHNL0",
[71] = "ASRC_CHNL1",
[72] = "ZERO_DET",
[73] = "DMA_IN_CH0",
[74] = "DMA_IN_CH1",
[75] = "DMA_IN_CH2",
[76] = "DMA_IN_CH3",
[77] = "DMA_IN_CH4",
[78] = "DMA_OUT_CH0",
[79] = "DMA_OUT_CH1",
[80] = "DMA_OUT_CH2",
[81] = "DMA_OUT_CH3",
[82] = "DMA_OUT_CH4",
[83] = "GPSPI2",
[84] = "GPSPI3",
[85] = "AES",
[86] = "SHA",
[87] = "ECC",
[88] = "ECDSA",
[89] = "KM",
[22] = "LP_PERI_PMS",
[23] = "CPU_FROM_CPU_0",
[24] = "CPU_FROM_CPU_1",
[25] = "CPU_FROM_CPU_2",
[26] = "CPU_FROM_CPU_3",
[27] = "BUS_MONITOR",
[28] = "CORE0_TRACE",
[29] = "CORE1_TRACE",
[30] = "CACHE",
[31] = "CPU_PERI_TIMEOUT",
[32] = "GPIO_INTERRUPT_PRO",
[33] = "GPIO_INTERRUPT_2",
[34] = "PAU",
[35] = "HP_PERI_TIMEOUT",
[36] = "HP_APM_M0",
[37] = "HP_APM_M1",
[38] = "HP_APM_M2",
[39] = "HP_APM_M3",
[40] = "HP_APM_M4",
[41] = "HP_MEM_APM_M0",
[42] = "HP_MEM_APM_M1",
[43] = "HP_MEM_APM_M2",
[44] = "HP_MEM_APM_M3",
[45] = "CPU_APM_M0",
[46] = "CPU_APM_M1",
[47] = "CPU_APM_M2",
[48] = "CPU_APM_M3",
[49] = "HP_PERI_PMS",
[50] = "MODEM_PERI_PMS",
[51] = "CPU_PERI_PMS",
[52] = "MSPI",
[53] = "I2S",
[54] = "UHCI0",
[55] = "UART0",
[56] = "UART1",
[57] = "LEDC",
[58] = "TWAI0",
[59] = "TWAI0_TIMER",
[60] = "USB_SERIAL_JTAG",
[61] = "RMT",
[62] = "I2C_EXT0",
[63] = "I2C_EXT1",
[64] = "TG0_T0",
[65] = "TG0_WDT",
[66] = "TG1_T0",
[67] = "TG1_WDT",
[68] = "SYSTIMER_TARGET0",
[69] = "SYSTIMER_TARGET1",
[70] = "SYSTIMER_TARGET2",
[71] = "APB_ADC",
[72] = "PWM0",
[73] = "PWM1",
[74] = "PCNT",
[75] = "PARL_IO_TX",
[76] = "PARL_IO_RX",
[77] = "USB_OTG11",
[78] = "ASRC_CHNL0",
[79] = "ASRC_CHNL1",
[80] = "ZERO_DET",
[81] = "DMA_IN_CH0",
[82] = "DMA_IN_CH1",
[83] = "DMA_IN_CH2",
[84] = "DMA_IN_CH3",
[85] = "DMA_IN_CH4",
[86] = "DMA_OUT_CH0",
[87] = "DMA_OUT_CH1",
[88] = "DMA_OUT_CH2",
[89] = "DMA_OUT_CH3",
[90] = "DMA_OUT_CH4",
[91] = "GPSPI2",
[92] = "GPSPI3",
[93] = "AES",
[94] = "SHA",
[95] = "ECC",
[96] = "ECDSA",
[97] = "KM",
};

100
components/soc/esp32h4/interrupts_beta5.c Normal file
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@@ -0,0 +1,100 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
[5] = "BT_BB",
[6] = "BT_BB_NMI",
[7] = "LP_TIMER",
[8] = "COEX",
[9] = "BLE_TIMER",
[10] = "BLE_SEC",
[11] = "I2C_MST",
[12] = "ZB_MAC",
[13] = "MODEM_APB_TIMEOUT",
[14] = "BT_MAC_INT1",
[15] = "PMU",
[16] = "EFUSE",
[17] = "LP_RTC_TIMER",
[18] = "LP_RTC_BLE_TIMER",
[19] = "LP_WDT",
[20] = "TOUCH",
[21] = "HUK",
[22] = "CPU_FROM_CPU_0",
[23] = "CPU_FROM_CPU_1",
[24] = "CPU_FROM_CPU_2",
[25] = "CPU_FROM_CPU_3",
[26] = "BUS_MONITOR",
[27] = "CORE0_TRACE",
[28] = "CORE1_TRACE",
[29] = "CACHE",
[30] = "CPU_PERI_TIMEOUT",
[31] = "GPIO_INTERRUPT_PRO",
[32] = "GPIO_INTERRUPT_2",
[33] = "PAU",
[34] = "HP_PERI_TIMEOUT",
[35] = "HP_APM_M0",
[36] = "HP_APM_M1",
[37] = "HP_APM_M2",
[38] = "HP_APM_M3",
[39] = "HP_APM_M4",
[40] = "CPU_APM_M0",
[41] = "CPU_APM_M1",
[42] = "CPU_APM_M2",
[43] = "CPU_APM_M3",
[44] = "MSPI",
[45] = "I2S",
[46] = "UHCI0",
[47] = "UART0",
[48] = "UART1",
[49] = "LEDC",
[50] = "TWAI0",
[51] = "TWAI0_TIMER",
[52] = "USB_SERIAL_JTAG",
[53] = "RMT",
[54] = "I2C_EXT0",
[55] = "I2C_EXT1",
[56] = "TG0_T0",
[57] = "TG0_WDT",
[58] = "TG1_T0",
[59] = "TG1_WDT",
[60] = "SYSTIMER_TARGET0",
[61] = "SYSTIMER_TARGET1",
[62] = "SYSTIMER_TARGET2",
[63] = "APB_ADC",
[64] = "PWM0",
[65] = "PWM1",
[66] = "PCNT",
[67] = "PARL_IO_TX",
[68] = "PARL_IO_RX",
[69] = "USB_OTG11",
[70] = "ASRC_CHNL0",
[71] = "ASRC_CHNL1",
[72] = "ZERO_DET",
[73] = "DMA_IN_CH0",
[74] = "DMA_IN_CH1",
[75] = "DMA_IN_CH2",
[76] = "DMA_IN_CH3",
[77] = "DMA_IN_CH4",
[78] = "DMA_OUT_CH0",
[79] = "DMA_OUT_CH1",
[80] = "DMA_OUT_CH2",
[81] = "DMA_OUT_CH3",
[82] = "DMA_OUT_CH4",
[83] = "GPSPI2",
[84] = "GPSPI3",
[85] = "AES",
[86] = "SHA",
[87] = "ECC",
[88] = "ECDSA",
[89] = "KM",
};

82
components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld Normal file
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@@ -0,0 +1,82 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
PROVIDE ( TRACE0 = 0x60000000 );
PROVIDE ( TRACE1 = 0x60001000 );
PROVIDE ( ASSIST_DEBUG = 0x60002000 );
PROVIDE ( INTPRI = 0x60005000 );
PROVIDE ( CACHE = 0x60008000 );
PROVIDE ( GPSPI2 = 0x60010000 );
PROVIDE ( GPSPI3 = 0x60011000 );
PROVIDE ( UART0 = 0x60012000 );
PROVIDE ( UART1 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( I2C0 = 0x60015000 );
PROVIDE ( I2C1 = 0x60016000 );
PROVIDE ( I2S0 = 0x60017000 );
PROVIDE ( PARL_IO = 0x60018000 );
PROVIDE ( MCPWM0 = 0x60019000 );
PROVIDE ( MCPWM1 = 0x6001A000 );
PROVIDE ( LEDC = 0x6001B000 );
PROVIDE ( TWAI0 = 0x6001C000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 );
PROVIDE ( RMT = 0x6001E000 );
PROVIDE ( RMTMEM = 0x6001E400 );
PROVIDE ( AHB_DMA = 0x6001F000 );
PROVIDE ( PAU = 0x60020000 );
PROVIDE ( SOC_ETM = 0x60021000 );
PROVIDE ( ADC = 0x60022000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */
PROVIDE ( MEM_MONITOR = 0x60025000 );
PROVIDE ( PVT = 0x60026000 );
PROVIDE ( PCNT = 0x60027000 );
PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
PROVIDE ( ZERO_DET = 0x60029000 );
PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 );
PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 );
PROVIDE ( USB_OTG_FS_PHY = 0x60080000 );
PROVIDE ( TIMERG0 = 0x60090000 );
PROVIDE ( TIMERG1 = 0x60091000 );
PROVIDE ( IO_MUX = 0x60092000 );
PROVIDE ( GPIO = 0x60093000 );
PROVIDE ( GPIO_EXT = 0x60093E00 );
PROVIDE ( SDM = 0x60093E00 );
PROVIDE ( GLITCH_FILTER = 0x60093ED8 );
PROVIDE ( GPIO_ETM = 0x60093F18 );
PROVIDE ( PCR = 0x60094000 );
PROVIDE ( SPIMEM0 = 0x60098000 );
PROVIDE ( SPIMEM1 = 0x60099000 );
PROVIDE ( INTMTX0 = 0x6009A000 );
PROVIDE ( INTMTX1 = 0x6009B000 );
PROVIDE ( HP_SYSTEM = 0x6009C000 );
PROVIDE ( HP_APM = 0x6009D000 );
PROVIDE ( CPU_APM = 0x6009E000 );
PROVIDE ( TEE = 0x6009F000 );
PROVIDE ( KEYMNG = 0x600A5000 );
PROVIDE ( AES = 0x600A6000 );
PROVIDE ( SHA = 0x600A7000 );
PROVIDE ( ECC = 0x600A8000 );
PROVIDE ( HMAC = 0x600A9000 );
PROVIDE ( ECDSA = 0x600AA000 );
PROVIDE ( HUK = 0x600B1000 );
PROVIDE ( LP_TEE = 0x600B1400 );
PROVIDE ( EFUSE = 0x600B1800 );
PROVIDE ( OTP_DEBUG = 0x600B1C00 );
PROVIDE ( TRNG = 0x600B2000 );
PROVIDE ( PMU = 0x600B2400 );
PROVIDE ( LP_AON = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_CLKRST = 0x600B3000 );
PROVIDE ( LPPERI = 0x600B3400 );
PROVIDE ( LP_IO_MUX = 0x600B3800 );
PROVIDE ( LP_GPIO = 0x600B3C00 );
PROVIDE ( LP_TIMER = 0x600B5000 );
PROVIDE ( LP_WDT = 0x600B5400 );
PROVIDE ( TOUCH_SENS = 0x600B5800 );
PROVIDE ( TOUCH_AON = 0x600B5C00 );
PROVIDE ( MODEM_SYSCON = 0x600C9C00 );
PROVIDE ( MODEM_LPCON = 0x600CF000 );

3
components/soc/esp32h4/ld/esp32h4.peripherals.ld
View File

@@ -54,7 +54,8 @@ PROVIDE ( INTMTX0 = 0x6009A000 );
PROVIDE ( INTMTX1 = 0x6009B000 );
PROVIDE ( HP_SYSTEM = 0x6009C000 );
PROVIDE ( HP_APM = 0x6009D000 );
PROVIDE ( CPU_APM = 0x6009E000 );
PROVIDE ( HP_MEM_APM_REG = 0x6009E000 );
PROVIDE ( CPU_APM = 0x6009E800 );
PROVIDE ( TEE = 0x6009F000 );
PROVIDE ( KEYMNG = 0x600A5000 );
PROVIDE ( AES = 0x600A6000 );

0
components/soc/esp32h4/register/soc/cpu_apm_reg.h → components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h
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0
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [7:0]; default: 1;
* Configure bit $n (0-7) to enable region $n.
* 0: disable
* 1: enable
*/
uint32_t region_filter_en:8;
uint32_t reserved_8:24;
};
uint32_t val;
} cpu_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of regionn_addr_start register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_start_l : HRO; bitpos: [12:0]; default: 0;
* Low 12 bit, start address of region n.
*/
uint32_t regionn_addr_start_l:13;
/** regionn_addr_start : R/W; bitpos: [24:13]; default: 0;
* Configures start address of region n.
*/
uint32_t regionn_addr_start:12;
/** regionn_addr_start_h : HRO; bitpos: [31:25]; default: 1;
* High 13 bit, start address of region n.
*/
uint32_t regionn_addr_start_h:7;
};
uint32_t val;
} cpu_apm_regionn_addr_start_reg_t;
/** Type of regionn_addr_end register
* Region address register
*/
typedef union {
struct {
/** regionn_addr_end_l : HRO; bitpos: [12:0]; default: 8191;
* Low 12 bit, end address of region n.
*/
uint32_t regionn_addr_end_l:13;
/** regionn_addr_end : R/W; bitpos: [24:13]; default: 4095;
* Configures end address of region n.
*/
uint32_t regionn_addr_end:12;
/** regionn_addr_end_h : HRO; bitpos: [31:25]; default: 1;
* High 13 bit, end address of region n.
*/
uint32_t regionn_addr_end_h:7;
};
uint32_t val;
} cpu_apm_regionn_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of regionn_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** regionn_r0_x : R/W; bitpos: [0]; default: 0;
* Configures the execution authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_x:1;
/** regionn_r0_w : R/W; bitpos: [1]; default: 0;
* Configures the write authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_w:1;
/** regionn_r0_r : R/W; bitpos: [2]; default: 0;
* Configures the read authority of REE_MODE 0 in region n.
*/
uint32_t regionn_r0_r:1;
uint32_t reserved_3:1;
/** regionn_r1_x : R/W; bitpos: [4]; default: 0;
* Configures the execution authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_x:1;
/** regionn_r1_w : R/W; bitpos: [5]; default: 0;
* Configures the write authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_w:1;
/** regionn_r1_r : R/W; bitpos: [6]; default: 0;
* Configures the read authority of REE_MODE 1 in region n.
*/
uint32_t regionn_r1_r:1;
uint32_t reserved_7:1;
/** regionn_r2_x : R/W; bitpos: [8]; default: 0;
* Configures the execution authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_x:1;
/** regionn_r2_w : R/W; bitpos: [9]; default: 0;
* Configures the write authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_w:1;
/** regionn_r2_r : R/W; bitpos: [10]; default: 0;
* Configures the read authority of REE_MODE 2 in region n.
*/
uint32_t regionn_r2_r:1;
/** regionn_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t regionn_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} cpu_apm_regionn_attr_reg_t;
/** Group: function control register */
/** Type of func_ctrl register
* APM function control register
*/
typedef union {
struct {
/** m0_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_func_en:1;
/** m1_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_func_en:1;
/** m2_func_en : R/W; bitpos: [2]; default: 1;
* PMS M2 function enable
*/
uint32_t m2_func_en:1;
/** m3_func_en : R/W; bitpos: [3]; default: 1;
* PMS M3 function enable
*/
uint32_t m3_func_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m0_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m0_exception_region:16;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} cpu_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m1_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m1_exception_region:16;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} cpu_apm_m1_exception_info1_reg_t;
/** Group: M2 status register */
/** Type of m2_status register
* M2 status register
*/
typedef union {
struct {
/** m2_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m2_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m2_status_reg_t;
/** Group: M2 status clear register */
/** Type of m2_status_clr register
* M2 status clear register
*/
typedef union {
struct {
/** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m2_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m2_status_clr_reg_t;
/** Group: M2 exception_info0 register */
/** Type of m2_exception_info0 register
* M2 exception_info0 register
*/
typedef union {
struct {
/** m2_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m2_exception_region:16;
/** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m2_exception_mode:2;
/** m2_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m2_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m2_exception_info0_reg_t;
/** Group: M2 exception_info1 register */
/** Type of m2_exception_info1 register
* M2 exception_info1 register
*/
typedef union {
struct {
/** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m2_exception_addr:32;
};
uint32_t val;
} cpu_apm_m2_exception_info1_reg_t;
/** Group: M3 status register */
/** Type of m3_status register
* M3 status register
*/
typedef union {
struct {
/** m3_exception_status : RO; bitpos: [1:0]; default: 0;
* Represents exception status.
* bit0: 1 represents authority_exception
* bit1: 1 represents space_exception
*/
uint32_t m3_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} cpu_apm_m3_status_reg_t;
/** Group: M3 status clear register */
/** Type of m3_status_clr register
* M3 status clear register
*/
typedef union {
struct {
/** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
* Configures to clear exception status.
*/
uint32_t m3_exception_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_m3_status_clr_reg_t;
/** Group: M3 exception_info0 register */
/** Type of m3_exception_info0 register
* M3 exception_info0 register
*/
typedef union {
struct {
/** m3_exception_region : RO; bitpos: [15:0]; default: 0;
* Represents exception region.
*/
uint32_t m3_exception_region:16;
/** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
* Represents exception mode.
*/
uint32_t m3_exception_mode:2;
/** m3_exception_id : RO; bitpos: [22:18]; default: 0;
* Represents exception id information.
*/
uint32_t m3_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} cpu_apm_m3_exception_info0_reg_t;
/** Group: M3 exception_info1 register */
/** Type of m3_exception_info1 register
* M3 exception_info1 register
*/
typedef union {
struct {
/** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
* Represents exception addr.
*/
uint32_t m3_exception_addr:32;
};
uint32_t val;
} cpu_apm_m3_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* Configures to enable APM M0 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* Configures to enable APM M1 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m1_apm_int_en:1;
/** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
* Configures to enable APM M2 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m2_apm_int_en:1;
/** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
* Configures to enable APM M3 interrupt.
* 0: disable
* 1: enable
*/
uint32_t m3_apm_int_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} cpu_apm_int_en_reg_t;
/** Group: Clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} cpu_apm_clock_gate_reg_t;
/** Group: Version control register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 38814240;
* Version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} cpu_apm_date_reg_t;
typedef struct {
volatile cpu_apm_region_filter_en_reg_t region_filter_en;
volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end;
volatile cpu_apm_regionn_attr_reg_t region0_attr;
volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end;
volatile cpu_apm_regionn_attr_reg_t region1_attr;
volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end;
volatile cpu_apm_regionn_attr_reg_t region2_attr;
volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end;
volatile cpu_apm_regionn_attr_reg_t region3_attr;
volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end;
volatile cpu_apm_regionn_attr_reg_t region4_attr;
volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end;
volatile cpu_apm_regionn_attr_reg_t region5_attr;
volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end;
volatile cpu_apm_regionn_attr_reg_t region6_attr;
volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start;
volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end;
volatile cpu_apm_regionn_attr_reg_t region7_attr;
uint32_t reserved_064[24];
volatile cpu_apm_func_ctrl_reg_t func_ctrl;
volatile cpu_apm_m0_status_reg_t m0_status;
volatile cpu_apm_m0_status_clr_reg_t m0_status_clr;
volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile cpu_apm_m1_status_reg_t m1_status;
volatile cpu_apm_m1_status_clr_reg_t m1_status_clr;
volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile cpu_apm_m2_status_reg_t m2_status;
volatile cpu_apm_m2_status_clr_reg_t m2_status_clr;
volatile cpu_apm_m2_exception_info0_reg_t m2_exception_info0;
volatile cpu_apm_m2_exception_info1_reg_t m2_exception_info1;
volatile cpu_apm_m3_status_reg_t m3_status;
volatile cpu_apm_m3_status_clr_reg_t m3_status_clr;
volatile cpu_apm_m3_exception_info0_reg_t m3_exception_info0;
volatile cpu_apm_m3_exception_info1_reg_t m3_exception_info1;
uint32_t reserved_108[4];
volatile cpu_apm_int_en_reg_t int_en;
uint32_t reserved_11c[439];
volatile cpu_apm_clock_gate_reg_t clock_gate;
volatile cpu_apm_date_reg_t date;
} cpu_apm_dev_t;
extern cpu_apm_dev_t CPU_APM;
#ifndef __cplusplus
_Static_assert(sizeof(cpu_apm_dev_t) == 0x800, "Invalid size of cpu_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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